Senior Logic Design Engineer (CPU Core Top)

The silicon computing development team is seeking passionate, driven, and intellectually curious computer/electrical engineers to deliver premium-quality designs once considered impossible. Our team is involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems ranging from traditional computing solutions to artificial intelligence and augmented reality. We are responsible for delivering cutting-edge, custom CPU and SoC designs that can perform complex and high-performance functions in an extremely efficient manner.ResponsibilitiesIn this role, you will:

• Be responsible for the logic design/RTL entry and timing closure of multiple blocks in a high-performance custom CPU/L2 Core sub-system

• Collaborate with the Core architects, physical design engineers and the power team to interpret the architectural intent to create power islands, annotate UPF files, design physical partitions, and insert feedthroughs signals
• Be responsible for "always-on" and any "glue" logic needed to integrate incoming IPs. Own Core top wrappers
• Drive closure of quality checks for all 3rd Party IP and 1st Party Core Top RTL: lint, CDC, RDC, Low Power Static Checks, synthesis smoke, etc

Qualifications

• Candidate must have at least a bachelor's degree in Electrical Engineering, Computer Engineering, or a related degree

• 5+ years of industry experience in logic design with a proven track record of delivering complex CPU or SoC IP's
• 3+ years working on complex CPU architectures and general computer architectures
• Familiarity with design flows and methodologies: lint, CDC, RDC, LP static, UPF, FEV, synthesis, timing and power analysis
• Strong understanding of sub-system design and challenges faced at the sub-system level

Preferred Qualifications:

• MS degree in Computer or Electrical Engineering and 10+ years of practical experience
• Substantial background in debugging designs as well as simulation environment s
• Experience with digital timing analysis, multiple clocks, power, synthesis, place-n-route
• Expertise in front - end design flows and methodologies and experience closing at sub-system level: RTL partitioning, third party IP integration, lint, DFT insertion , UPF annotation , synthesis and timing closure , System / Control Register integration, and 1 st order verification debug

• Scripting language , Python preferred

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form .
Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.
#MicrosoftCPUCore